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| ST10F167 16-BIT MCU WITH 128K BYTE FLASH MEMORY PRELIMINARY DATASHEET s s s s s s 10-Bit ADC PWM s s s s s s s s s s s s s s s s s s High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20MHz CPU Clock 500 ns Multiplication (16 x 16 bit), 1 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Clock Generation via on-chip PLL or via direct clock input Up to 16 MBytes Linear Address Space for Code and Data 2K Bytes On-Chip Internal RAM (IRAM) 2K Bytes On-Chip Extension RAM (XRAM) 128K Bytes On-Chip FLASH memory FLASH Memory organized into 4 banks independently erasable Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/ Data Buses Five Programmable Chip-Select Signals Hold- and Hold-Acknowledge Bus Arbitration Support 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns 16-Channel 10-bit A/D Converter with 9.7s Conversion Time Two 16-Channel Capture/Compare Units 16 Internal FLASH Memory 32 C PU-C ore 16 Internal R AM 16 PEC XRA M 16 Interrupt Controller 16 CAN W atchdog OSC. Port 4 Port 1 Port 0 GPT1 ASC usart External Bus Controller CAPCOM2 16 CAPCOM1 SSC GPT2 16 Port 2 8 16 8 BR G Port 3 15 BRG Port 7 8 Port 8 Port 6 8 Port 5 16 s s s s s s s s s 4-Channel PWM Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (Synchronous/ Asynchronous and High-Speed-Synchronous) On-Chip CAN 2.0B Interface with 15 Message Objects (Full-CAN/Basic-CAN) Programmable Watchdog Timer Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis Supported by development tools: C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 144-Pin PQFP Package May 1997 This is preliminary information on a new product indevelopment or undergoing evaluation. Details are subject to change without notice. 1/69 1 Table of Contents 1 2 3 4 5 6 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PIN DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 6.2 6.3 7 8 9 Flash Memory Programming And Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Flash Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Flash Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 CENTRAL PROCESSING UNIT (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CAPTURE/COMPARE (CAPCOM) UNITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 GENERAL PURPOSE TIMER (GPT) UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11 PWM MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13 A/D CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15 CAN-MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16 PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 17 INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 18 BOOTSTRAP LOADER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 19 SPECIAL FUNCTION REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 20 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 20.1 20.2 20.3 20.4 20.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 20.5.1 20.5.2 20.5.3 20.5.4 20.5.5 20.5.6 20.5.7 Test Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Direct Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . 50 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2/62 2 20.5.8 20.5.9 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 20.5.10 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 21 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 22 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3/62 ST10F167 1 INTRODUCTION ty and enhanced IO-capabilities. It also provides on-chip high-speed RAM and clock generation via PLL. The ST10F167 is a flash derivative of the SGS-THOMSON ST10 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance with high peripheral functionali- Figure 1.1 Logic Symbol VDD XTAL1 XTAL2 RSTIN RSTOUT VAREF VAGND NMI EA READY ALE RD WR/WRL Port 5 16-bit VSS Port 0 16-bit Port 1 16-bit Port 2 16-bit ST10F167 Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit 4/69 3 2 P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO VDD VSS P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28I0 P7.5/CC29I0 P7.6/CC30I0 P7.7/CC31I0 P5.0AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9 PIN DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ST10F167 VAREF VAGND P5.10/AN10/T6EUD P5.11/AN11/T5EUD P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4EUD P5.15/AN15/T2EUD VSS VDD P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO VSS VDD P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IOEX2IN P2.11/CC11IOEX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN/T7IN P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN VSS VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS NMI RSTOUT RSTIN VSS XTAL1 XTAL2 VDD P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VSS VDD P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 POH.7/AD15 POH.6/AD14 POH.5/AD13 POH.4/AD12 POH.3/AD11 POH.2/AD10 POH.1/AD9 VSS VDD 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 ST10F167 POH.0/AD8 POL.7/AD7 POL.6/AD6 POL.5/AD5 POL.4/AD4 POL.3/AD3 POL.2AD2 POL.A/AD1 POL.0/AD0 EA ALE READY WR/WRL RD VSS VDD P4.7/A23 P4.6/A22/CAN_T XD P4.5/A21/CAN_R X D P4.4/A20 P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 VPP VSS VDD P3.15/CLKOUT P3.13/SCLK P3.12/BHE/WRH P3.11/RXD0 P3.10/TXD0 P3.9/MTSR P3.8/MRST P3.7/T2IN P3.6/T3IN 5/69 3 ST10F167 Table 2.1 Symbol P6.0 - P6.7 Pin Definitions and Functions Pin Number 1-8 Input (I) Output (O) I/O Function Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The following Port 6 pins also serve for alternate functions: P6.0 CS0 Chip Select 0 Output ... ... ... P6.4 CS4 Chip Select 4 Output P6.5 HOLD External Master Hold Request Input P6.6 HLDA Hold Acknowledge Output P6.7 BREQ Bus Request Output Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 8 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out ... ... ... P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 7 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: P7.0 POUT0 PWM Channel 0 Output ... ... ... P7.3 POUT3 PWM Channel 3 Output P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out ... ... ... P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out 1 ... 5 6 7 8 P8.0 - P8.7 9 - 16 O ... O I O O I/O 9 ... 16 P7.0 -P7.7 19 - 26 I/O ... I/O I/O 19 ... 22 23 ... 26 O ... O I/O ... I/O 6/69 3 ST10F167 Table 2.1 Symbol P5.0-P5.15 Pin Definitions and Functions (cont'd) Pin Number 27 - 36 39 - 44 Input (I) Output (O) I I Function Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out ... ... ... P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out, EX0IN Fast External Interrupt 0 Input ... ... ... P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out, EX7IN Fast External Interrupt 7 Input T7IN CAPCOM2 Timer T7 Count Input 39 40 41 42 43 44 P2.0-P2.15 47 - 54 57 - 64 I I I I I I I/O 47 ... 54 57 ... 64 I/O ... I/O I/O I ... I/O I I 7/69 3 ST10F167 Table 2.1 Symbol P3.0P3.13, P3.15 Pin Definitions and Functions (cont'd) Pin Number 65 - 70, 73 - 80, 81 Input (I) Output (O) I/O I/O I/O Function Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bitwise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE Ext. Memory High Byte Enable Signal, WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line P4.5 A21 Segment Address Line, CAN_RxD CAN Receive Data Input P4.6 A22 Segment Address Line, CAN_TxD CAN Transmit Data Output P4.7 A23 Most Significant Segment Addr. Line External Memory Read Strobe. RD is activated for every external instruction or data read access. 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 85 - 92 I O I O I I I I I/O I/O O I/O O O I/O O I/O P4.0 -P4.7 85 90 91 92 RD 95 O O I O O O O 8/69 3 ST10F167 Table 2.1 Symbol WR/WRL Pin Definitions and Functions (cont'd) Pin Number 96 Input (I) Output (O) O Function External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the ST10F167 to begin instruction execution out of external memory. A high level forces execution out of the internal Flash Memory. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width:8-bit 16-bit P0L.0 - P0L.7:D0 - D7D0 - D7 P0H.0 - P0H.7:I/O D8 - D15 Multiplexed bus modes: Data Path Width:8-bit 16-bit P0L.0 - P0L.7:AD0 - AD7AD0 - AD7 P0H.0 - P0H.7:A8 - A15AD8 - AD15 READY 97 I ALE 98 O EA 99 I PORT0: P0L.0P0L.7, P0H.0P0H.7 I/O 100-107 108, 111-117 9/69 3 ST10F167 Table 2.1 Symbol PORT1: P1L.0 - P1L.7, P1H.0 P1H.7 Pin Definitions and Functions (cont'd) Pin Number Input (I) Output (O) I/O 118 - 125 128 - 135 Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4 CC24IO CAPCOM2: CC24 Capture Input P1H.5 CC25IO CAPCOM2: CC25 Capture Input P1H.6 CC26IO CAPCOM2: CC26 Capture Input P1H.7 CC27IO CAPCOM2: CC27 Capture Input XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F167. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. Internal Reset Indication Output. This pin is set to a low level when the part is executing, either a hardware, a software or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F167 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Reference voltage for the A/D converter. Reference ground for the A/D converter. Flash programming voltage. This pin accepts the programming voltage for the on-chip flash EPROM of the ST10F167. 132 133 134 135 XTAL1 XTAL2 138 137 I I I I I O RSTIN 140 I RSTOUT 141 O NMI 142 I VAREF VAGND VPP 37 38 84 - 10/69 3 ST10F167 Table 2.1 Symbol VDD Pin Definitions and Functions (cont'd) Pin Number 46, 82, 136 17, 56, 72, 93, 109,126, 144 45, 83, 139 18, 55, 71, 94, 110,127, 143 Input (I) Output (O) Function Digital Supply Voltage for internal circuitry: + 5 V during normal operation and idle mode. 2.5 V during power down mode Digital Supply Voltage for port drivers: + 5 V during normal operation and idle mode - VSS - Digital Ground for internal circuitry. Digital Ground for port drivers. 11/69 3 ST10F167 3 FUNCTIONAL DESCRIPTION ferent on-chip components and of the advanced, high bandwidth internal bus structure of the ST10F167. The architecture of the ST10F167 combines the advantages of both RISC and CISC processors and an advanced peripheral subsystem. The following block diagram gives an overview of the dif- Figure 3.1 Block Diagram 16 Internal FLASH Memory 32 CPU-Core 16 Internal RAM 16 Watchdog XRAM 16 PEC Interrupt Controller OSC. 16 CAN Module Port 0 16 10-Bit ADC Ext. Bus Controller GPT1 T2 T3 T4 GPT2 T5 T6 ASC (USART) SSC PWM CAPCOM CAPCOM 2 1 Port 2 Port 4 8 Port 1 16 T7 T8 T0 T1 16 ... Port 5 BRG Port 3 BRG Port 7 ... ... Port 8 Port 6 8 16 15 8 8 VR02060C 12/69 3 ST10F167 4 MEMORY ORGANIZATION 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for other/future members of the ST10 family. 2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code. The XRAM is accessed like external memory and cannot be used for the system stack or register banks, and is not bit-addressable. The XRAM allows 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. The memory space of the ST10F167 is configured in a Von-Neumann architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The ST10F167 provides 128KBytes of on-chip flash memory. 2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 5 EXTERNAL BUS CONTROLLER Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable. This gives the choice of a wide range of different types of memories and external peripherals. In addition, different address ranges may be accessed with different bus characteristics. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported via a particular `Ready' function. A HOLD/HLDA protocol is available for bus arbitration. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines. If an address space of 16 MBytes is used, it outputs all 8 address lines. All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: * * * * 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output. 13/69 3 ST10F167 6 FLASH MEMORY The first 32K bytes of the FLASH memory are located in segment 0 (0h to 007FFFh) during reset, and include the reset and interrupt vectors. The rest of the FLASH memory is mapped in segments 1 and 2 (018000h to 02FFFFh). For flexibility, the first 32K bytes of the FLASH memory may be remapped to segment 1 (010000h to 017FFFh) during initialization. This allows the interrupt vectors to be programmed from the external memory, while retaining the common routines and constants that are programmed into the FLASH memory. The ST10F167 provides 128KBytes of on-chip, electrically erasable and re-programmable Flash EPROM. The flash memory is organized in 32 bit wide blocks. This allows double word instructions to be fetched in one machine cycle. The flash memory can be used for both code and data storage. The flash memory is organised into four banks of sizes 8K, 24K, 48K and 48Kbytes (table 6.1). Each of these banks can be erased independently. This prevents unnecessary re-programming of the whole flash memory when only a partial re-programming is required. Table 6.1 Bank 0 1 2 3 FLASH Memory Bank Organisation Addresses (Segment 0) Size (bytes) 48K 48K 24K 8K 000000h to 07FFFh and 018000h to 01BFFFh 01C000h to 027FFFh 028000h to 02DFFFh 02E000h to 02FFFFh 6.1 Flash Memory Programming And Erasure tion is indicated by a flag. A second flag indicates that the V PP voltage was correct for the whole programming cycle. This guarantees that a good write/erase operation has been carried out. The FLASH parameters are detailed below. The FLASH memory is programmed using the PRESTO F Program Write algorithm. Erasure of the FLASH memory is performed in the program mode using the PRESTO F Erase algorithm. Timing of the Write/Erase cycles is automatically generated by a programmable timer and comple- Table 6.2 Parameter Flash Parameters Units sec sec cycles volts 11.4 Min 12.8 Typical 12.8 0.5 1000 Max 1250 30 12.6 Word Programming Time Bank Erasing Time Endurance Flash Vpp 14/69 3 ST10F167 6.2 Flash Control Register (FCR) FWMSET must be set to "1". Reset condition of FWMSET is "0". b14-b10 = Reserved: these bits are reserved for future development, they must be written to "0". b9-b8 = BE0,1: Bank erase select. These bits select the Flash memory bank to be erased. The physical addresses of bank 0 depends on the which Flash memory map has been chosen. In Flash operating modes, other than the erasing mode, these bits are not significant. At reset BE1,0 are set to "00". b7 = WDWW: Word/double word write. This bit determines the word width used for programming operations: 16-bit (WDWW = 0) or 32-bit (WDWW = "1"). In Flash operation modes, other than the programming mode, this bit is not significant. At reset, WDWW is set to "0". b6-b5 = CKCTL0,1: Flash Timer Clock Control. These two bits control the width (TPRG) of the programming or erase pulses applied to the Flash memory cells during the operation. TPRG varies in an inverse ratio to the clock frequency. To avoid putting the Flash memory under critical stress conditions, the width of one single programming or erase pulse and the programming or erase time, must not exceed defined values. Thus the maximum number of programming or erase attempts, depends on the system clock frequency. RESET state: 00. b4 = VPPRIV: VPP Revelation bit. This read-only bit reflects the state of the VPP voltage in the Flash writing mode. If VPPRIV is set to "0", this indicates that VPP is below the threshold necessary for reliable programming. The normal reaction to this indication is to check the VPP power supply and to then repeat the intended operation. If the VPP voltage is above a sufficient margin, VPPRIV will be set to "1". The reset state of the VPPRIV bit depends on the state of the external VPP voltage at the VPP pin. In the standard operation mode, the FLASH memory can be accessed in the same way as the normal mask-programmable on-chip ROM. All, appropriate, direct and indirect addressing modes can be used for reading the FLASH memory. All programming or erase operations are controlled via a 16-bit register, the FCR. The FCR is not an SFR or GPR. To prevent inadvertent writing to the FLASH memory, the FCR is locked and inactive during the standard operation mode. The FLASH memory writing mode must be entered, before a valid access to the FCR is provided. This is done via a special key code instruction sequence. The FCR is virtually mapped into the active address space of the Flash memory. It can only be accessed with direct 16-bit (mem) addressing modes. Since the FCR is neither byte, nor bit-addressable, only word operand instructions can be used for FCR accesses. By default, the FCR can be accessed with any even address from 000000h to 07FFFEh and 018000h to 02FFFEh. If the first 32K byte Block of the FLASH memory is mapped to segment 1, the corresponding even FCR addresses are 010000h to 017FFEh. Note that DPP referencing and DPP contents must be considered for FCR accesses. If an FCR access is attempted via an odd address, an illegal operand access hardware trap will occur. FCR Flash Control Register Reset Condition: 0000h (Read) b15 = FWMSET: Flash Writing Mode Set. This bit is set to "1" automatically once the Flash writing mode is entered. To exit from the Flash writing mode, FWMSET must be set to "0". Since only word values can be written to FCR, care must be taken that FWMSET is not cleared inadvertently. Therefore, for any command written to FCR (except for the return to the Flash standard mode), 15/69 3 ST10F167 b3 = FCVPP: Flash VPP control bit. This read-only bit indicates that the VPP voltage fell below the valid threshold value during a Flash programming or erase operation. If FCVPP is set to "1" after such an operation has finished, it can mean that the operation was not successful. The VPP power supply should be checked and the operation repeated. If FCVPP is set to "0", no critical discontinuity in VPP occurred. At reset FCVPP is set to "0". b2 = FBUSY: Flash busy bit. This read-only bit indicates that a Flash programming or erase operation is in progress. FBUSY is set to "1" by hardware, as soon as the programming or erase command is given. At reset FBUSY is set to "0". Note that this bit position is also occupied by the writeonly bit RPROT. b2 = RPROT: Protection enable bit. This bit set at 1, anded with the OTP protection bit, disables any access to the Flash, by instructions fetched from the external memory space, or from the internal RAM. This write-only bit, is only significant if the general Flash memory protection is enabled. If the protection is enabled, the setting of RPROT determines whether the Flash protection is active (RPROT="1") or inactive (RPROT="0"). RPROT is the only FCR bit which can be modified even in the Flash standard operation mode, but only by an in- struction executed from the Flash memory itself. At reset, RPROT is set to "1". Note that this bit position is also occupied by the read-only bit FBUSY. b1 = FEE: Flash erase/program selection. This bit selects the Flash write operation to be performed: erase (FEE="1") or programming (FEE="0"). Together with bits FWE and FWMSET, bit FEE determined the operation mode of the Flash memory. Note that setting bits FWE and FEE causes the corresponding Flash operation mode to be selected but does not launch the execution of the selected operation. If bit FWE was set to "0", the setting of FEE is insignificant. At reset, FEE is set to "0". b0 = FWE: Flash write/read enable. This bit determines whether FLASH write operations are enabled (FWE=1) or disabled (FWE=0). By definition, a FLASH write operation can be either programming or erasure. Together with bits FEE and FWMSET, bit FWE determines the operation mode of the Flash memory. Note that setting bits FWE and FEE causes the corresponding Flash operation mode to be selected but does not launch the execution of the selected operation. If bit FWE was set to "1", any read access on a Flash memory location means a particular program-verify or erase-verify read operation. Flash write operations are disabled at reset. 6.3 Flash Memory Security Memory. If the security option is set, the FLASH memory can only be accessed from a program within the FLASH memory area. This protection can only be disabled by instructions executed from the FLASH memory. Security and reliability have been enhanced by built-in features: a key code sequence is used to enter the Write/Erase mode preventing false write cycles, a programmable option (set by the programming board) prevents access to the FLASH memory from the internal RAM or from External 16/69 3 ST10F167 Figure 6.1 PRESTO F Write Algorithm =0 PCOUNT=PNmax? PCOUNT=PCOUNT+1 VR02057A 17/69 3 ST10F167 Figure 6.2 PRESTO F Erase Algorithm =0 PCOUNT=ENmax? PCOUNT=PCOUNT+1 VR02057B 18/69 3 ST10F167 7 CENTRAL PROCESSING UNIT (CPU) CPU Block Diagram Figure 7.1 CPU SP STKOV STKUN Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs MDH MLD Mul./Div.-HW Bit-Mask Gen. R15 16 FLASH ROM 32 General ALU 16-Bit Barrel-Shift Context Ptr R0 ADDRSE L 1 ADDRSE L 2 ADDRSE L 3 ADDRSE L 4 Code Seg. Ptr. Purpose Registers Internal RAM 2KByte R15 16 R0 The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the ST10F167's instructions can be executed in one machine cycle. This requires 100ns at 20MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized for speed: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. The `Jump Cache' pipeline optimization, reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. The CPU includes an actual register context. This consists of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. 19/69 3 ST10F167 An efficient instruction set allows maximum use of the CPU. The instruction set is classified into the following groups: * * * * * * Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction * * * * * * Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes exist. 8 INTERRUPT SYSTEM ST10F167 has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 8.1 shows all of the possible ST10F167 interrupt sources and the corresponding hardwarerelated interrupt flags, vectors, vector locations and trap (interrupt) numbers With an interrupt response time from 250ns to 600ns (in the case of internal program execution), the ST10F167 reacts quickly to the occurrence of non-deterministic events The architecture of the ST10F167 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In a standard interrupt service, program execution is suspended and a branch to the interrupt vector table is performed. For a PEC service, just one cycle is `stolen' from the current CPU activity. A PEC service is a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is decremented for each PEC service, except for the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are suited to, for example, the transmission or reception of blocks of data. The 20/69 3 ST10F167 Table 8.1 Interrupt Sources, Flags, Vector and Trap Numbers Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR T1IR T7IR T8IR Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE T1IE T7IE T8IE Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT T1INT T7INT T8INT Vector Location 00'0040h 00'0044h 00'0048h 00'004Ch 00'0050h 00'0054h 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h 00'00C8h 00'00CCh 00'00D0h 00'00D4h 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00E0h 00'0110h 00'0114h 00'0118h 00'0080h 00'0084h 00'00F4h 00'00F8h Trap Number 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 44h 45h 46h 20h 21h 3Dh 3Eh Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 21/69 3 ST10F167 Table 8.1 Interrupt Sources, Flags, Vector and Trap Numbers (cont'd) Request Flag T2IR T3IR T4IR T5IR T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR Enable Flag T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE Interrupt Vector T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT Vector Location 00'0088h 00'008Ch 00'0090h 00'0094h 00'0098h 00'009Ch 00'00A0h 00'00A4h 00'00A8h 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch Trap Number 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 47h 2Bh 2Ch 2Dh 2Eh 2Fh 3Fh 40h 41h 42h 43h Source of Interrupt or PEC Service Request GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 CAN Interface X-Peripheral Node X-Peripheral Node PLL Unlock Note: Two X-Peripheral nodes can accept interrupt requests from integrated X-Bus peripherals. Nodes, where no XPeripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit. The ST10F167 provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, `Hardware Traps'. Hardware traps cause an immediate nonmaskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts Table 8.2 shows all of the possible exceptions or error conditions that can arise during run-time. 22/69 3 ST10F167 Table 8.2 Exceptions or Error Conditions During Runtime Trap Flag Trap Vector RESET RESET RESET NMI STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS NMITRAP STOTRP STUTRP BTRAP BTRAP BTRAP BTRAP BTRAP Vector Location 00'0000h 00'0000h 00'0000h 00'0008h 00'0010h 00'0018h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [2Ch - 3Ch] Any [00'0000h - 00'01FCh] in steps of 4h Trap Number 00h 00h 00h 02h 04h 06h 0Ah 0Ah 0Ah 0Ah 0Ah [0Bh - 0Fh] Any [00h - 7Fh] Trap Priority III III III II II II I I I I I Current CPU Priority Exception Condition Reset Functions: *Hardware Reset *Software Reset *Watchdog Timer Overflow Class A Hardware Traps: *Non-Maskable Interrupt *Stack Overflow *Stack Underflow Class B Hardware Traps: *Undefined Opcode *Protected Instruction Fault *Illegal Word Operand Access *Illegal Instruction Access *Illegal External Bus Access Reserved Software Traps *TRAP Instruction 23/69 3 ST10F167 9 CAPTURE/COMPARE (CAPCOM) UNITS ters, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin (except for CC24...CC27) to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken, based on the selected compare mode. The CAPCOM units support generation and control of timing sequences on up to 32 channels. It has a maximum resolution of 400 ns at 20MHz system clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers, provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several pre-scaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Both of the two capture/compare register arrays contain 16 dual purpose capture/compare regis- Table 9.1 Compare Mode Function Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Compare Modes Mode 0 Mode 1 Mode 2 Mode 3 Double Register Mode 24/69 3 ST10F167 Figure 9.1 CAPCOM Unit Block Diagram ), *) 12 outputs on CAPCOM2 25/69 3 ST10F167 10 GENERAL PURPOSE TIMER (GPT) UNIT registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4, triggered, either by an external signal, or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 160 ns (@ 20MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The GPT unit is a flexible multifunctional timer/ counter structure. It may be used for many different time-related tasks such as: event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer, in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation: Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the `gate' level on an external input pin. Each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400ns (@ 20MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may be altered dynamically by an external signal on a port pin (TxEUD) to facilitate, for example, position tracking. Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer overflow/underflow. The state of these latches may be output on port pins (TxOUT) for time-out monitoring by external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture 26/69 3 ST10F167 Figure 10.1 T2EUD Block Diagram of GPT1 U/D GPT1 Timer T2 2n n=3...10 Interrupt Request CPU Clock T2IN T2 Mode Control Reload Capture CPU Clock 2n n=3...10 T3EUD T3 Mode Control T3OUT GPT1 Timer T3 U/D T3OTL T3IN Capture T4IN CPU Clock T4 Mode Control 2n n=3...10 Reload Interrupt Request Interrupt Request GPT1 Timer T4 T4EUD U/D 27/69 3 ST10F167 Figure 10.2 Block Diagram of GPT2 T5EUD U/D CPU Clock T5IN 2n n=2...9 T5 Mode Control GPT2 Timer T5 Clear Capture Interrupt Request CAPIN GPT2 CAPREL Interrupt Request Reload Interrupt Request Toggle FF T4IN CPU Clock 2n n=2...9 T6 Mode Control GPT1 Timer T6 U/D T60TL T6OUT to CAPCOM Timers T4EUD 11 PWM MODULE signals is from 4.8 Hz to 1 MHz (referred to a CPU clock of 20 MHz), depending on the resolution of the PWM output signal. The level of the output signals is selectable and the PWM module can generate interrupt requests. The Pulse Width Modulation Module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the PWM 28/69 3 ST10F167 12 WATCHDOG TIMER pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Therefore, time intervals between 25s and 420ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz). The Watchdog Timer is a fail-safe mechanism. It limits the maximum malfunction time of the controller The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. In this way the chip's start-up procedure is always monitored. The software must be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT 13 A/D CONVERTER ware intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without the overhead of interrupt routines for each data transfer. After each reset and also during normal operation, the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to the changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle. They do not affect the normal operation of the A/D converter. A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip for analog signal measurement. It uses a successive approximation method. The sample time (for loading the capacitors) and conversion time is programmable and can be modified for the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT). When the result of a previous conversion has not been read from the result register at the time the next conversion is complete, either an interrupt request is generated, or the next conversion is suspended, until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F167 supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without soft- 29/69 3 ST10F167 14 SERIAL CHANNELS guish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock. The shift clock can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. `framing error detection' recognizes data frames with missing stop bits. An overrun error is generated if the last character received was not read out of the receive buffer register, on the reception of a new character. Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces. An Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). ASC0 supports full-duplex asynchronous communication up to 625 KBaud and half-duplex synchronous communication up to 2.5 Mbaud @ 20MHz system clock. The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20MHz system clock. Two dedicated baud rate generators are used to set up standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception, 3 separate interrupt vectors are provided for each serial channel. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distin- 15 CAN-MODULE tering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The CAN-Module uses two pins to interface to a bus transceiver. The integrated CAN-Module performs the autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active). The on-chip CAN-Module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The module provides full CAN functionality for up to 15 message objects. Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance fil- 30/69 3 ST10F167 16 PARALLEL PORTS All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/ 19/17...A16 in systems where segmentation is enabled to access more than 64KBytes of memory.Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. All port lines that are not used for these alternate functions may be used as general purpose IO lines. The ST10F167 provides up to 77 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/ O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like). The special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. 31/69 3 ST10F167 17 INSTRUCTION SET SUMMARY conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the "ST10 Programming Manual".. The table below lists the instruction set of the ST10F167. More detailed information such as address modes, instruction operation, parameters for Table 17.1 ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) Instruction Set Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 2/4 2/4 2/4 4 4 4 Mnemonic BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B 32/69 3 ST10F167 Table 17.1 JBC JNBS Instruction Set (cont'd) Description Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (assumes NMI-pin low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2 Mnemonic CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP 18 BOOTSTRAP LOADER strap loader mode is activated, an instruction fetch is performed from the test ROM regardless of the configuration selected with the EBC0, EBC1 and BUSACT pins. The reset vector in the test ROM branches to the self-test program, while the NonMaskable Interrupt vector (NMI) branches to the Boot-strap loader routine. The self-test routine execution time is approximately 10ms. It terminates with a software reset instruction (SRST), where the chip is restarted ac- To activate the Boot-strap loader, a hardware reset with RSTIN pin low and an external pull-up resistor connected to the ALE pin, is applied. This forces the chip into a special test mode. The program execution starts from 1K bytes ROM, mapped from 0 to 3FF hex which is not accessible in normal execution mode. This test ROM contains a one-time programmable flash EPROM, loaded with a self-test program plus the Boot-strap loader program. When the Boot- 33/69 3 ST10F167 cording to the EBC0, EBC1 and BUSACT pin configurations. The state of the ALE pin is not taken into account for software reset. To trigger the Boot-strap loader program, it is necessary to activate the Non Maskable Interrupt by forcing a low level on the NMI pin before the end of the self-test routine The identification byte sent by the ST10F167 is D5h. Note that the bootstrap loader of all ST10 devices which include identification registers will return D5h as the identification byte. The startup code loaded with bootstrap loader will dump identification registers for complete chip identification from the host. 19 SPECIAL FUNCTION REGISTER OVERVIEW An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). The following table lists all ST10F167 SFRs in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Table 19.1 Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC b BUSCON0 b BUSCON1 b BUSCON2 b BUSCON3 b BUSCON4 b CAPREL CC0 CC0IC CC1 CC1IC CC2 CC2IC b b b b b Special Function Register List Physical Address FF98h FFA0h FEA0h F0A0h E FE18h FE1Ah FE1Ch FE1Eh FF9Ah FF0Ch FF14h FF16h FF18h FF1Ah FE4Ah FE80h FF78h FE82h FF7Ah FE84h FF7Ch 8-Bit Address CCh D0h 50h 50h 0Ch 0Dh 0Eh 0Fh CDh 86h 8Ah 8Bh 8Ch 8Dh 25h 40h BCh 41h BDh 42h BEh Description A/D Converter End of Conversion Interrupt Cont Reg A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D Converter Overrun Error Interrupt Control Reg Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Register CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Register CAPCOM Register 2 CAPCOM Register 2 Interrupt Control Register Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0XX0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 34/69 3 ST10F167 Table 19.1 Name CC3 CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 CC7IC CC8 CC8IC CC9 CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC20 CC20IC b b b b b b b b b b b b b b b b b b Special Function Register List (cont'd) Physical Address FE86h FF7Eh FE88h FF80h FE8Ah FF82h FE8Ch FF84h FE8Eh FF86h FE90h FF88h FE92h FF8Ah FE94h FF8Ch FE96h FF8Eh FE98h FF90h FE9Ah FF92h FE9Ch FF94h FE9Eh FF96h FE60h F160h E FE62h F162h E FE64h F164h E FE66h F166h E FE68h F168h E 8-Bit Address 43h BFh 44h C0h 45h C1h 46h C2h 47h C3h 48h C4h 49h C5h 4Ah C6h 4Bh C7h 4Ch C8h 4Dh C9h 4Eh CAh 4Fh CBh 30h B0h 31h B1h 32h B2h 33h B3h 34h B4h Description CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Register CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Register CAPCOM Register 5 CAPCOM Register 5 Interrupt Control Register CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Register CAPCOM Register 7 CAPCOM Register 7 Interrupt Control Register CAPCOM Register 8 CAPCOM Register 8 Interrupt Control Register CAPCOM Register 9 CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 CAPCOM Register 11 Interrupt Control Register CAPCOM Register 12 CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 CAPCOM Register 14 Interrupt Control Register CAPCOM Register 15 CAPCOM Register 15 Interrupt Control Register CAPCOM Register 16 CAPCOM Register 16 Interrupt Control Register CAPCOM Register 17 CAPCOM Register 17 Interrupt Control Register CAPCOM Register 18 CAPCOM Register 18 Interrupt Control Register CAPCOM Register 19 CAPCOM Register 19 Interrupt Control Register CAPCOM Register 20 CAPCOM Register 20 Interrupt Control Register Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 35/69 3 ST10F167 Table 19.1 Name CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CC31IC CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 CP CRIC CSP DP0L DP0H DP1L b b b b b b b b b b b b b b b b b b b b b b b Special Function Register List (cont'd) Physical Address FE6Ah F16Ah E FE6Ch F16Ch E FE6Eh F16Eh E FE70h F170h E FE72h F172h E FE74h F174h E FE76h F176h E FE78h F178h E FE7Ah F184h E FE7Ch F18Ch E FE7Eh F194h E FF52h FF54h FF56h FF58h FF22h FF24h FF26h FF28h FE10h FF6Ah FE08h F100h E F102h E F104h E 8-Bit Address 35h B5h 36h B6h 37h B7h 38h B8h 39h B9h 3Ah BAh 3Bh BBh 3Ch BCh 3Dh C2h 3Eh C6h 3Fh CAh A9h AAh ABh ACh 91h 92h 93h 94h 08h B5h 04h 80h 81h 82h Description CAPCOM Register 21 CAPCOM Register 21 Interrupt Control Register CAPCOM Register 22 CAPCOM Register 22 Interrupt Control Register CAPCOM Register 23 CAPCOM Register 23 Interrupt Control Register CAPCOM Register 24 CAPCOM Register 24 Interrupt Control Register CAPCOM Register 25 CAPCOM Register 25 Interrupt Control Register CAPCOM Register 26 CAPCOM Register 26 Interrupt Control Register CAPCOM Register 27 CAPCOM Register 27 Interrupt Control Register CAPCOM Register 28 CAPCOM Register 28 Interrupt Control Register CAPCOM Register 29 CAPCOM Register 29 Interrupt Control Register CAPCOM Register 30 CAPCOM Register 30 Interrupt Control Register CAPCOM Register 31 CAPCOM Register 31 Interrupt Control Register CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 5 CAPCOM Mode Control Register 6 CAPCOM Mode Control Register 7 CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (read only) P0L Direction Control Register P0H Direction Control Register P1L Direction Control Register Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FC00h 0000h 0000h 00h 00h 00h 36/69 3 ST10F167 Table 19.1 Name DP1H DP2 DP3 DP4 DP6 DP7 DP8 DPP0 DPP1 DPP2 DPP3 EXICON MDC MDH MDL ODP2 ODP3 ODP6 ODP7 ODP8 ONES P0L P0H P1L P1H P2 P3 P4 P5 P6 P7 P8 PECC0 PECC1 PECC2 PECC3 b b b b b b b b b b b b b b b b b b b b b b b b b Special Function Register List (cont'd) Physical Address F106h E FFC2h FFC6h FFCAh FFCEh FFD2h FFD6h FE00h FE02h FE04h FE06h F1C0h E FF0Eh FE0Ch FE0Eh F1C2h E F1C6h E F1CEh E F1D2h E F1D6h E FF1Eh FF00h FF02h FF04h FF06h FFC0h FFC4h FFC8h FFA2h FFCCh FFD0h FFD4h FEC0h FEC2h FEC4h FEC6h 8-Bit Address 83h E1h E3h E5h E7h E9h EBh 00h 01h 02h 03h E0h 87h 06h 07h E1h E3h E7h E9h EBh 8Fh 80h 81h 82h 83h E0h E2h E4h D1h E6h E8h EAh 60h 61h 62h 63h Description P1H Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register Port 7 Direction Control Register Port 8 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Port 7 Open Drain Control Register Port 8 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Port 6 Register (8 bits) Port 7 Register (8 bits) Port 8 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register Reset Value 00h 0000h 0000h 00h 00h 00h 00h 0000h 0001h 0002h 0003h 0000h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h FFFFh 00h 00h 00h 00h 0000h 0000h 00h XXXXh 00h 00h 00h 0000h 0000h 0000h 0000h 37/69 3 ST10F167 Table 19.1 Name PECC4 PECC5 PECC6 PECC7 PICON PP0 PP1 PP2 PP3 PSW PT0 PT1 PT2 PT3 PW0 PW1 PW2 PW3 PWMCON0b PWMCON1b PWMIC RP0H S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON b SSCEIC SSCRB b b b b b b b b b Special Function Register List (cont'd) Physical Address FEC8h FECAh FECCh FECEh F1C4h E F038h E F03Ah E F03Ch E F03Eh E FF10h F030h E F032h E F034h E F036h E FE30h FE32h FE34h FE36h FF30h FF32h F17Eh E F108h E FEB4h FFB0h FF70h FEB2h FF6Eh F19Ch E FEB0h FF6Ch FE12h F0B4h E FFB2h FF76h F0B2h E 8-Bit Address 64h 65h 66h 67h E2h 1Ch 1Dh 1Eh 1Fh 88h 18h 19h 1Ah 1Bh 18h 19h 1Ah 1Bh 98h 99h BFh 84h 5Ah D8h B8h 59h B7h CEh 58h B6h 09h 5Ah D9h BBh 59h Description PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port Input Threshold Control Register PWM Module Period Register 0 PWM Module Period Register 1 PWM Module Period Register 2 PWM Module Period Register 3 CPU Program Status Word PWM Module Up/Down Counter 0 PWM Module Up/Down Counter 1 PWM Module Up/Down Counter 2 PWM Module Up/Down Counter 3 PWM Module Pulse Width Register 0 PWM Module Pulse Width Register 1 PWM Module Pulse Width Register 2 PWM Module Pulse Width Register 3 PWM Module Control Register 0 PWM Module Control Register 1 PWM Module Interrupt Control Register System Startup Configuration Register (Rd. only) Serial Channel 0 Baud Rate Generator Reload Reg Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXh 0000h 0000h 0000h XXh 0000h 0000h 00h 0000h FC00h 0000h 0000h 0000h XXXXh 38/69 3 ST10F167 Table 19.1 Name SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON b T0 T01CON T0IC T0REL T1 T1IC T1REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC T7 T78CON T7IC T7REL T8 T8IC T8REL TFR b b b b b b b b b b b b b b b b b b b Special Function Register List (cont'd) Physical Address FF74h F0B0h E FF72h FE14h FE16h FF12h FE50h FF50h FF9Ch FE54h FE52h FF9Eh FE56h FE40h FF40h FF60h FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h FE48h FF48h FF68h F050h E FF20h F17Ah E F054h E F052h E F17Ch E F056h E FFACh 8-Bit Address BAh 58h B9h 0Ah 0Bh 89h 28h A8h CEh 2Ah 29h CFh 2Bh 20h A0h B0h 21h A1h B1h 22h A2h B2h 23h A3h B3h 24h A4h B4h 28h 90h BEh 2Ah 29h BFh 2Bh D6h Description SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Control Register CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Control Register CAPCOM Timer 7 Interrupt Control Register CAPCOM Timer 7 Reload Register CAPCOM Timer 8 Register CAPCOM Timer 8 Interrupt Control Register CAPCOM Timer 8 Reload Register Trap Flag Register Reset Value 0000h 0000h 0000h FA00h FC00h 0xx0h1) 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 39/69 3 ST10F167 Table 19.1 Name WDT WDTCON XP0IC XP1IC XP2IC XP3IC ZEROS b b b b b Special Function Register List (cont'd) Physical Address FEAEh FFAEh F186h E F18Eh E F196h E F19Eh E FF1Ch 8-Bit Address 57h D7h C3h C7h CBh CFh 8Eh Description Watchdog Timer Register (read only) Watchdog Timer Control Register CAN Module Interrupt Control Register X-Peripheral 1 Interrupt Control Register X-Peripheral 2 Interrupt Control Register PLL Interrupt Control Register Constant Value 0's Register (read only) Reset Value 0000h 000Xh2) 0000h 0000h 0000h 0000h 0000h Notes 1:The system configuration is selected during reset. 2:Bit WDTR indicates a watchdog timer triggered reset. 3:The Interrupt Control Registers XPnIC, control interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit. 40/69 3 ST10F167 20 ELECTRICAL CHARACTERISTICS 20.1 Absolute Maximum Ratings Ambient temperature under bias (TA): ST10F167.................................................................. -40 +85 C to - Storage temperature (TST)................................................................................................... 65 to +150 C Voltage on VDD pins with respect to ground (VSS).................................................................. -0.5 to +6.5 V Voltage on any pin with respect to ground (VSS) ............................................................. -0.3 VDD +0.3 V to Input current on any pin during overload condition.............................................................. -10 to +10 mA Absolute sum of all input currents during overload condition........................................................ |100 mA| Power dissipation............................................................................................................................... 1.5 W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VIN The parameters listed in the Electrical Characteristics tables, 20.1 to 20.9, represent the characteristics of the ST10F167 and its demands on the system. Where the ST10F167 logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics, is included in the "Symbol" column. Where the external system must provide signals with their respective timing characteristics to the ST10F167, the symbol "SR" for System Requirement, is included in the "Symbol" column. 41/69 3 ST10F167 20.3 DC Characteristics VDD = 5 V 5%, VSS = 0, fCPU = 20MHz, Reset active, T A = -40 to +85 C Table 20.1 DC Parametric Parameter Symbol VILSR VILSSR VIHSR VIH1SR VIH2SR VIHSSR HYS VOLCC Limit Values min. - 0.5 - 0.5 0.2 VDD + 0.9 0.6 VDD 0.7 VDD 0.8 VDD - 0.2 400 - max. 0.2 VDD - 0.1 2.0 VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5 0.45 Unit V V V V V V mV V Test Condition - - - - - - - IOL = 2.4 mA Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage, all except RSTIN and XTAL1 (TTL) Input high voltage RSTIN Input high voltage XTAL1 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs) 1) VOL1CC VOHCC - 0.45 - V V IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA 0.45V < VIN < VDD 0.45V < VIN < VDD 5) 8) - VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max 0.9 VDD 2.4 0.9 VDD 2.4 - - - 50 - -500 - 500 - -500 VOH1CC IOZ1CC IOZ2CC IOVSR RRSTCC 4) - 1 1 5 250 -40 - 30 - -40 - V V A A mA k A A A A A A Input leakage current (Port 5) Input leakage current (all other) Overload current RSTIN pullup resistor Read/Write inactive current Read/Write active current ALE inactive current ALE active current 4) 4) 4) 4) IRWH IRWL IALEL IALEH IP6H IP6L 2) 3) 2) 3) 2) 3) Port 6 inactive current Port 6 active current 4) 42/69 3 ST10F167 Table 20.1 DC Parametric (cont'd) Parameter Symbol 4) Limit Values min. max. -10 - 20 Unit A A A pF mA mA A A mA Test Condition VIN = VIHmin VIN = VILmax 0 V < VIN < VDD PORT0 configuration current XTAL1 input current Pin capacitance (digital inputs/outputs) Power supply current Idle mode supply current 5) IP0H IP0L 2) 3) - -100 - - - - - - IIL CC CIO CC ICC IID IPD IPPR IPPW 10 120 + 5 * fCPU 40 + 2 * fCPU 100 200 50 f = 1MHz TA = 25 C RSTIN = VIL fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6) VDD = 5.25 V 7) VPP < VDD at 20MHz 32-Bit programming VPP = 12V Power-down mode supply current VPP Read Current VPP Write Current VPP during Write/Read VPP 11.4 12.6 V Notes 1:This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2:The maximum current may be drawn while the respective signal line remains inactive. 3:The minimum current must be drawn in order to drive the respective signal line active. 4:This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. 5:Not 100% tested, guaranteed by design characterization. 6:The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 20 MHz CPU clock with all outputs disconnected and all inputs at V IL or VIH. 7:This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 8:Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV < VSS-0.5V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. 9:Power Down Current is to be defined. 43/69 3 ST10F167 Figure 20.1 I [mA] Supply/Idle Current as a Function of Operating Frequency 150 ICCmax 100 ICCtyp IIDmax 50 IIDtyp 10 5 10 15 20 fCPU [MHz] 44/69 3 ST10F167 20.4 A/D Converter Characteristics VDD = 5 V 5%, VSS = 0 V, TA = -40 to +85 C 4.0 V VAREF VDD+0.1 V, VSS-0.1 V VAGND VSS+0.2 V Table 20.2 A/D Converter Characteristics Symbol VAIN SR CC CC Limit Values min. VAGND - - - - - - max. VAREF 2 tSC 14 tCC + tS + 4TCL +3 Unit V 1) 2) 4) 3) 4) LSB k k pF 5) Test Condition Parameter Analog input voltage range Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance tS tC TUE CC RAREF SR RASRC SR CAIN CC tCC / 165 - 0.25 tS / 330 - 0.25 33 tCC in [ns] 6) 7) tS in [ns] 2) 7) 7) Sample time and conversion time of the ST10F167's ADC are programmable. Table 20.3 shows the timing calculations. Table 20.3 ADCON.15|14 (ADCTC) 00 01 10 11 Sample and Conversion Time Calculations Conversion clock tCC TCL * 24 Reserved, do not use TCL * 96 TCL * 48 ADCON.13|12 (ADSTC) 00 01 10 11 Sample clock tSC tCC tCC * 2 tCC * 4 tCC * 8 Notes 1:VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FF H, respectively. 2:During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tSC depend on programming and can be taken from the table above. 3:This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the table above. 4:This parameter depends on the ADC control logic. It is not a real maximum value, but rather a 45/69 3 ST10F167 fixum. 5:TUE is tested at VAREF=5.0V, VAGND=0V, VDD=4.9V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see I OV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB. 6:During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results from the programmed conversion timing. 7:Not 100% tested, guaranteed by design characterization. 46/69 3 ST10F167 20.5 AC Characteristics 20.5.1 Test Waveforms Figure 20.2 Input Output Waveforms 2.4V 0.2VDD+0.9 0.2VDD+0.9 Test Points 0.45V 0.2VDD-0.1 0.2V DD-0.1 AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 20.3 Float Waveforms V OH VOH -0.1V Timing Reference Points V OL +0.1V VOL V Load +0.1V V Load VLoad -0.1V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,but begins to float whena 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). 47/69 3 ST10F167 20.5.2 Definition of Internal Timing The internal operation of the ST10F167 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see Figure 20.4). The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be taken into consideration when calculating the timings for the ST10F167. Figure 20.4 Generation Mechanisms for the CPU Clock Phase Locked Loop Operation fXTAL fCPU TCL TCL Direct Clock Drive fXTAL fCPU TCL TCL 20.5.3 Direct Drive When pin P0.15 (P0H.7) is low (`0') during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock f XTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCL min = 1 f X TA L *DC min DC = duty cycle For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: 2TCL = 1/fXTAL. Note:The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL * DCmax) instead of TCLmin. 48/69 3 ST10F167 20.5.4 Phase Locked Loop When pin P0.15 (P0H.7) is high (`1') during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by 4 (i.e. fCPU = fXTAL * 4). With every fourth transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of f CPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so that it remains locked to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation DN: TCLmi n = TCL NOM * ( 1 - lD N l ) 100 D N = ( 4 - N 15 ) [ % ] where N = number of consecutive TCLs and 1 N 40. So for a period of 3 TCLs (i.e. N = 3): D 3 = 4 - 3 15 = 3.8% TCLmin = TCLN OM x ( 1 - 3.8 100 ) = TCL NOM x 0.962 ( 24.1nsec@f CP U = 20MHz ) This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Figure 20.5 Approximated Maximum PLL Jitter This approximated formula is valid for 1 N 40 and 10MHz fCPU 20MHz. Max.jitter [%] 4 3 2 1 8 2 4 16 32 N 49/69 3 ST10F167 20.5.5 External Clock Drive XTAL1 VDD = 5 V 5%, VSS = 0 V, TA = -40 to +85 C Table 20.4 External Clock Drive Characteristics Parameter Symbol Direct Drive 1:1 min. 50 1) 25 25 - - max. 1000 - - 10 10 PLL 1:4 min. 200 6 6 - - max. 333 - - 10 10 Unit ns ns ns ns ns Oscillator period High time Low time Rise time Fall time 1) tOSC t1 t2 t3 t4 SR SR SR SR SR Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. Figure 20.6 External Clock Drive XTAL1 t1 t3 t4 VIH2 t2 VIL tOSC 20.5.6 Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 20.5 Memory Cycle Variable Definition Description Symbol Values TCL * ALE Extension Memory Cycle Time Waitstates Memory Tristate Time tA tC tF 50/69 3 ST10F167 20.5.7 Multiplexed Bus VDD = 5 V 5%,VSS = 0 V, TA = -40 to +85 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates) Table 20.6 Multiplexed Bus Characteristics Symbol Max. CPU Clock = 20 MHz min. max. - - - - - 5 30 - - 5 + tC 55 + tC 40 + tA + tC 60 + 2tA + tC - 35 + tF - - - - 15 + tA 0 + tA 15 + tA 15 + tA -10 + tA - - 25 + tC 65 + tC - - - - 0 - 15 + tC 35 + tF 35 + tF 35 + tF Variable CPU Clock 1/2TCL = 1 to 20 MHz min. TCL - 10 + tA TCL - 25 + tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - 2TCL - 25 + tC 3TCL - 10 + tC - - - - 0 - 2TCL - 35 + tC 2TCL - 15 + tF 2TCL - 15 + tF 2TCL - 15 + tF max. - - - - - 5 TCL + 5 - - 2TCL - 45 + tC 3TCL - 20 + tC 3TCL - 35 + tA + tC 4TCL - 40 + 2tA + tC - 2TCL - 15 + tF - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Parameter ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR t5 CC t6 CC t7 CC t8 CC t9 CC t10 CC t11 CC t12 CC t13 CC t14 SR t15 SR t16 SR t17 SR t18 SR t19 SR t22 SR t23 CC ALE rising edge after RD, t25 CC WR Address hold after RD, WR t27 CC 51/69 3 ST10F167 Table 20.6 Multiplexed Bus Characteristics (cont'd) Symbol Max. CPU Clock = 20 MHz min. -5 - tA - 60 + tF 20 + tA -5 + tA - - - - 40 + tC 65 + tC 35 + tC 0 - 30 + tF 30 + tF max. 10 - tA 45 + tC + 2tA - - - 0 25 15 + tC 50 + tC - - - - 30 + tF - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. -5 - tA - 3TCL - 15 + tF TCL - 5 + tA -5 + tA - - - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 max. 10 - tA 3TCL - 30 + tC + 2tA - - - 0 TCL 2TCL - 35 + tC 3TCL - 25 + tC - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS t38 CC t39 SR t40 CC t42 CC t43 CC t44 CC t45 CC t46 SR t47 SR t48 CC t49 CC t50 CC t51 SR t52 SR t54 CC t56 CC - 2TCL - 20 + tF 2TCL - 20 + tF - 2TCL - 20 + tF - 52/69 3 ST10F167 Figure 20.7 External Memory Cycle:Multiplexed Bus, With Read/Write Delay, Normal ALE t5 ALE t16 t25 t38 CSx t39 t40 A23-A16 (A15-A8) BHE t17 Address t27 t6 Read Cycle BUS t7 t54 t19 t18 Address Data In t8 RD t10 t14 t44 t12 t46 t48 t51 t52 t42 RdCSx Write Cycle BUS Address t23 Data Out t8 WR, WRL, WRH t10 t56 t22 t12 t50 t48 t42 WrCSx t44 53/69 3 ST10F167 Figure 20.8 External Memory Cycle:Multiplexed Bus, Extended ALE With Read/Write Delay, t5 ALE t16 t38 t39 t25 t40 CSx A23-A16 (A15-A8) BHE t17 Address t27 t6 Read Cycle BUS Address t7 t54 t19 t18 Data In t8 RD t10 t14 t44 t12 t46 t48 t51 t52 t42 RdCSx Write Cycle BUS Address Data Out t23 t8 WR, WRL, WRH t10 t56 t22 t12 t50 t48 t42 WrCSx t44 54/69 3 ST10F167 Figure 20.9 External Memory Cycle:Multiplexed Bus, No Read/Write Delay, Normal ALE t5 ALE t16 t25 t38 CSx t39 t40 A23-A16 (A15-A8) BHE t17 Address t27 t6 Read Cycle BUS t7 t54 t19 t18 Address Data In t9 RD t11 t15 t13 t51 t52 t43 RdCSx t45 t47 t49 Write Cycle BUS Address t23 Data Out t9 WR, WRL, WRH t56 t11 t22 t13 t45 t50 t49 t43 WrCSx 55/69 3 ST10F167 Figure 20.10 External Memory Cycle:Multiplexed Bus, No Read/Write Delay, Extended ALE t5 ALE t16 t38 t39 t25 t40 CSx A23-A16 (A15-A8) BHE t17 Address t27 t6 Read Cycle BUS Address t7 t54 t19 t18 Data In t9 RD t11 t15 t13 t51 t52 t43 RdCSx t45 t47 t49 Write Cycle BUS Address Data Out t23 t56 t9 WR, WRL, WRH t11 t13 t22 t43 WrCSx t45 t49 t50 56/69 3 ST10F167 20.5.8 Demultiplexed Bus VDD = 5 V 5%,VSS = 0 V, TA = -40 to +85 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates) Table 20.7 Demultiplexed Bus Characteristics Symbol Max. CPU Clock = 20 MHz min. max. - - - - - - 5 + tC 55 + tC 40 + tA + tC 60 + 2tA + tC - 35 + tF 15 + tF - - - - 10 - tA 45 + tC + 2tA 15 + tA 0 + tA 15 + tA -10 + tA 25 + tC 65 + tC - - - - 0 - - 15 + tC 15 + tF -10 + tF -2.5 + tF -5 - tA - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. TCL - 10 + tA TCL - 25 + tA TCL - 10 + tA -10 + tA 2TCL - 25 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL - 35 + tC TCL - 10 + tF -10 + tF -2.5 + tF -5 - tA - max. - - - - - - 2TCL - 45 + tC 3TCL - 20 + tC 3TCL - 35 + tA + tC 4TCL - 40 + 2tA + tC - 2TCL - 15 + tF TCL - 10 + tF - - - - 10 - tA 3TCL - 30 + tC + 2tA ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay) Data float after RD rising edge (no RW-delay) Data valid to WR Data hold after WR ALE rising edge after RD, WR t5 t6 t8 t9 CC CC CC CC t12 CC t13 t14 t15 t16 t17 t18 t20 t21 t22 t24 t26 CC SR SR SR SR SR SR SR CC CC CC CC CC SR Address hold after RD, WR t28 ALE falling edge to CS t38 CS low to Valid Data In t39 57/69 3 ST10F167 Table 20.7 Demultiplexed Bus Characteristics (cont'd) Symbol Max. CPU Clock = 20 MHz min. 10 + tF 20 + tA -5 + tA - - 40 + tC 65 + tC 35 + tC 0 - - -10 + tF 10 + tF max. - - - 15 + tC 50 + tC - - - - 30 + tF 5 + tF - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. TCL - 15 + tF TCL - 5 + tA -5 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - - -10 + tF TCL - 15 + tF max. - - - 2TCL - 35 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS t41 t42 t43 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57 CC CC CC SR SR CC CC CC SR SR SR CC CC 58/69 3 ST10F167 Figure 20.11 External Memory Cycle:Demultiplexed Normal ALE Bus, With Read/Write Delay, t5 ALE t16 t26 t38 CSx t39 t41 A23-A16 A15-A0 BHE t17 Address t28 t6 Read Cycle BUS (D15-D8) D7-D0 t55 t20 t18 Data In t8 RD t14 t12 t51 t53 t42 RdCSx t46 t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t24 Data Out t57 t8 t12 t42 t50 t48 t22 WrCSx 59/69 3 ST10F167 Figure 20.12 External Memory Cycle:Demultiplexed Extended ALE Bus, With Read/Write Delay, t5 ALE t16 t38 t39 t26 t41 CSx A23-A16 A15-A0 BHE t17 Address t28 t6 Read Cycle BUS (D15-D8) D7-D0 t55 t20 t18 Data In t8 RD t14 t12 t51 t53 t42 RdCSx t46 t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t24 Data Out t57 t8 t12 t42 t50 t48 t22 WrCSx 60/69 3 ST10F167 Figure 20.13 External Memory Cycle:Demultiplexed Bus, No Read/Write Delay, Normal ALE t5 ALE t16 t26 t38 CSx t39 t41 A23-A16 A15-A0 BHE t17 Address t28 t6 Read Cycle BUS (D15-D8) D7-D0 t55 t21 t18 Data In t9 RD t15 t43 t13 t47 t49 t51 t68 RdCSx Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t9 WR, WRL, WRH t57 t22 t13 t50 t49 t43 WrCSx 61/69 ST10F167 Figure 20.14 External Memory Cycle:Demultiplexed Extended ALE Bus, No Read/Write Delay, t5 ALE t16 t38 t39 t26 t41 CSx A23-A16 A15-A0 BHE t17 Address t28 t6 Read Cycle BUS (D15-D8) D7-D0 t55 t21 t18 Data In t9 RD t15 t13 t51 t68 t43 RdCSx t47 t49 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t57 t9 t22 t13 t43 t50 t49 WR, WRL, WRH WrCSx 62/69 ST10F167 20.5.9 CLKOUT and READY VDD = 5 V 5%, VSS = 0 V, T A = -40 to +85 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF Table 20.8 CLKOUT and READY Characteristics Symbol Max. CPU Clock = 20 MHz min. max. 50 - - 5 10 10 + tA - - - - - 0 + tc + 2tA + tF 2) Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL TCL - 5 TCL - 10 - - -5 + tA 30 0 2TCL + 15 15 0 0 max. 2TCL - - 5 10 10 + tA - - - - - TCL - 25 + tc + 2tA + tF 2) Unit ns ns ns ns ns ns ns ns ns ns ns ns t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60 CC CC CC CC CC CC SR SR SR SR SR SR 50 20 15 - - -5 + tA 30 0 65 15 0 0 Notes 1:These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2:Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and 2tc refer to the next bus cycle, tF refers to the current bus cycle. 63/69 ST10F167 Figure 20.15 CLKOUT and READY Running cycle 1) READY waitstate MUX/Tristate 6) CLKOUT t32 t30 t34 t33 t31 t29 7) ALE Command RD, WR 2) t35 Sync READY 3) t36 t35 3) t36 t58 Async READY 3) t59 t58 3) 5) t59 t60 4) t37 see 6) Notes 1:Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2:The leading edge of the respective command depends on RW-delay. 3:READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4:READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5:If the Asynchronous READY signal does not fulfil the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfil t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6:Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7:The next external bus cycle may start here. 64/69 ST10F167 20.5.10 External Bus Arbitration VDD = 5 V 5%, VSS = 0 V, T A = -40 to +85 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF Table 20.9 External Bus Arbitration Characteristics Symbol Max. CPU Clock = 20 MHz min. max. - 20 20 20 25 20 25 35 - - - -5 - -5 Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 35 - - - -5 - -5 max. - 20 20 20 25 20 25 ns ns ns ns ns ns ns Unit Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive t61 t62 t63 t64 t65 t66 t67 SR CC CC CC CC CC CC 65/69 ST10F167 Figure 20.16 External Bus Arbitration, Releasing the Bus CLKOUT t61 HOLD t63 HLDA 1) t62 BREQ 2) t64 CSx (On P6.x) 3) t66 Other Signals 1) Notes 1:The ST10F167 will complete the currently running bus cycle before granting bus access. 2:This is the first possibility for BREQ to get active. 3:The CS outputs will be resistive high (pullup) after t64. 66/69 ST10F167 Figure 20.17 External Bus Arbitration (Regaining the Bus) CLKOUT 2) t61 HOLD t62 HLDA t62 BREQ t62 1) t63 t65 CSx (On P6.x) t67 Other Signals Notes 1:This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F167 requesting the bus. 2:The next ST10F167 driven bus cycle may start here. 67/69 ST10F167 21 PACKAGE MECHANICAL DATA Package Outline PQFP144 (28 x 28 mm) Figure 21.1 mm D im min A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 30.95 27.90 0.25 3.17 0.22 0.13 30.95 27.90 31.20 28.00 22.75 0.65 31.20 28.00 22.75 0.80 1.60 0(min), 7(max) 0.95 0.026 31.45 28.10 1.219 1.098 3.42 3.67 0.38 0.23 31.45 28.10 ty max 4.07 0.010 0.125 0.009 0.005 1.129 1.098 min inches ty max 0.106 0.315 0.144 0.015 0.009 1.228 1.120 0.896 0.021.228 1.102 0.896 0.031 0.063 1.238 1.106 1.238 1.106 0.037 Number of Pins VR02061A N1 144 22 ORDERING INFORMATION Salestype Temperature range -40C to 85C Package PQFP144 (28 x 28) ST10F167-Q6 68/69 Notes Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-TH OMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THO MSON Microelectronics. (c)1997 SGS-TH OMSON Microelectronics - All rights reserved. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 69/69 4 |
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